Chemical-mechanical polishing/planarization (CMP) techniques, compositions, and apparatus therefor have been developed for providing smooth topographies, particularly on the surfaces of layers deposited on semiconductor substrates during integrated circuit (IC) device manufacture. In such instances, rough surface topography results when metal conductor lines are formed over a substrate containing device circuitry, e.g., inter-level metallization patterns comprising a plurality of electrically conductive lines which may, inter alia, serve to interconnect discrete devices formed within the substrate. The metal conductor lines are insulated from each other and from vertically adjacent interconnection levels by thin layers of dielectric insulation material, termed “interlayer dielectric” (abbreviated as “ILD”) or “intermetal dielectric” (abbreviated as “IMD”), and openings formed through the ILD or IMD layers provide electrical interconnection and access between successive such interconnection levels. In fabricating such type devices including multiple interconnection and ILD or IMD layers, it is desirable that the metallic and dielectric insulation layers have a smooth topography, inasmuch as it is very difficult to photolithographically image and pattern layers applied to rough surfaces. CMP techniques and methodology can also be employed for removing different layers of material from the surface of a semiconductor substrate, as for example, following via hole formation in an ILD or IMD layer, when a metallization layer is deposited to fill the via hole and then CMP is used to form planar metal via plugs embedded in the ILD layer.
Briefly, CMP processes utilized in semiconductor device manufacture involve mounting a thin flat workpiece, e.g., a semiconductor wafer substrate, on a carrier or polishing head, with the surface to be polished/planarized being exposed. The substrate surface is then urged against a wetted polishing/planarizing surface, i.e., a pad, under controlled mechanical pressure, chemical, and temperature conditions. In addition, the carrier head may translate or rotate to provide relative motion between the substrate and polishing pad surfaces. A polishing composition, typically but not exclusively, in the form of a slurry containing a polishing agent, such as finely-dimensioned alumina (Al2O3), silica (SiO2), or ceria (CeO2) particles, is used for facilitating material removal. Typically, the polishing composition additionally contains a number of chemicals, depending upon the material(s) to be polished, including pH adjusting and stabilizing agents, as well as chemical oxidizing agents for chemically reacting with various components of the surface being polished/planarized. The combination of mechanical and chemical interaction of surface material during the polishing/planarization process results in superior polishing/planarization of the surface being worked on, vis-à-vis other polishing/planarization techniques.
CMP, as described above, may be conducted with either a high or a low selectivity with respect to the particular layer or material being removed by the polishing/planarization process. When CMP is performed with high selectivity, the removal rate of the selected material is significantly higher than that of other material(s) exposed at the surface of the workpiece being polished. Conversely, when CMP is performed with low selectivity, each material present on or at the workpiece surface being polished is removed at substantially the same rate.
The escalating requirements for high integration density and performance associated with the manufacture of ultra-large scale integration semiconductor devices necessitate responsive changes in interconnection (“back end”) technology. As a consequence, copper (Cu) and Cu-based alloys (the symbol Cu as employed in the present disclosure refers to high purity, elemental copper and the expression “Cu-based alloys” refers to alloys containing at least about 80 wt. % copper), have received considerable attention as replacement materials for replacing conventional metal interconnect materials, e.g., aluminum (Al) and Al-based alloys, in view of, inter alia, their low cost and increased resistance to electromigration.
However, due to the tendency for deleterious diffusion of Cu atoms and/or ions into neighboring ILD or IMD (e.g., silicon dioxide, SiO2) and semiconductor (e.g., silicon, Si) layers, it is necessary to provide a thin diffusion barrier layer between Cu and Cu-based alloy metallization features and adjacent ILD or IMD and/or semiconductor layers. Currently, tantalum (Ta)-containing layers, e.g., elemental Ta and tantalum nitride (TaN), are most commonly employed for this purpose.
As for CMP processing for polishing/planarization of such Cu or Cu-based alloy metallization/interconnection systems including Ta or TaN diffusion barrier layers which effectively encapsulate the Cu or Cu-based alloy metallization features, a high selectivity CMP process, such as described above, advantageously removes the Cu or Cu-based alloy with little or no concurrent loss of the Ta or TaN barrier layer or ILD or IMD material (e.g., SiO2), whereas a low selectivity CMP process, as described above, disadvantageously incurs a significant concurrent loss of Ta, TaN, and SiO2. However, conventional high selectivity CMP processing frequently results in excessive polishing of portions of the metal features on wide metal lines, e.g., 50 μm wide Cu lines, leading to formation of concavities or depressions in the polished surface, termed “dishing”. However, if a high selectivity CMP process is performed only on very narrow metal lines, e.g., Ta-containing vertical barriers typically about 0.025 μm thick between dielectric insulator and Cu features, Ta-containing barrier layer dishing is negligible. The advantages of high selectivity CMP of Ta-containing barrier layers are not only low oxide loss and low metal loss, but also substantial reduction of dishing which typically occurs in the previous polishing steps. On the other hand, current CMP processes and commercially available slurries for barrier layer removal are limited as to useful chemical composition of the slurry because of the relatively inert nature of Ta and its compounds, such as TaN, and consequently, rely predominantly on strong mechanical abrasion. Stated somewhat differently, the currently available CMP processes and compositions with high solids concentrations for workpieces with Ta-containing barrier layers have either:
(a) very poor selectivity among the barrier layer (e.g., Ta- or TaN-based), metal layer (Cu-based), and the ILD or IMD layer (silicon oxide-based), resulting in excessive concurrent removal of the metal and ILD or IMD layers; or
(b) a very slow barrier layer removal rate at low pH, which is adverse with respect to surface roughness and Cu corrosion.
Accordingly, there exists a need for a simple and reliable method and composition for performing CMP in the manufacture of semiconductor IC devices employing Cu-based metallization systems including Ta-containing barrier layers, which method and composition are free of the disadvantages and drawbacks associated with the conventional CMP methodologies described above, and are fully compatible with the economic and throughput requirements of large-scale, automated semiconductor manufacture processing.
The present invention addresses and solves the above-described problems attendant upon the manufacture of semiconductor IC devices including Cu-based metallization systems with Ta-containing barrier layers according to conventional CMP methodology utilizing abrasive slurries and is fully compatible with all other mechanical and chemical aspects of CMP processing for polishing/planarization.